Modern x64 Architectures and the Cache
References ▼
WikiChip
[1]38:25
Intel
Intel Intrinsics Guide
[2]1:34:39
uops.info
[3]1:34:39
Intel
Intel® 64 and IA-32 Architectures Software Developer Manuals
[4]1:34:39
Wikichip
Zen - Microarchitectures - AMD
[5]1:49:21
TechPowerUp
AMD Ryzen Threadripper 1900X Core Configuration Detailed
[6]1:53:12
Wikipedia
Extreme ultraviolet lithography
[7]1:53:12[11]2:10:11
Taiwan Semiconductor Manufacturing Company Limited
[8]1:55:06
AnandTech
Intel Details Manufacturing through 2023: 7nm, 7+, 7++, with Next Gen Packaging
[9]1:55:06
Wikipedia
Transistor count
[10]1:55:06
Wikipedia
MESI protocol
[12]2:43:38
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Casey Muratori
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4:55vateferfout handmade_hero Hello, it's nice to finally be able to catch a stream live
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4:55vateferfout handmade_hero Hello, it's nice to finally be able to catch a stream live
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4:55vateferfout handmade_hero Hello, it's nice to finally be able to catch a stream live
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5:11ivereadthesequel handmade_hero Hey Casey, it's my birthday today and I'm glad to catch some Handmade Hero on it! Woo!
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5:11ivereadthesequel handmade_hero Hey Casey, it's my birthday today and I'm glad to catch some Handmade Hero on it! Woo!
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5:11ivereadthesequel handmade_hero Hey Casey, it's my birthday today and I'm glad to catch some Handmade Hero on it! Woo!
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5:48Desire a sponsor for Handmade Hero
5:48Desire a sponsor for Handmade Hero
5:48Desire a sponsor for Handmade Hero
6:54simpalaxy Q: You mentioned on Twitter being interested in a hiring process that includes an option for people to record themselves doing their normal programming work. Is there a way you think the industry could be led to feasibly adopt that?
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6:54simpalaxy Q: You mentioned on Twitter being interested in a hiring process that includes an option for people to record themselves doing their normal programming work. Is there a way you think the industry could be led to feasibly adopt that?
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6:54simpalaxy Q: You mentioned on Twitter being interested in a hiring process that includes an option for people to record themselves doing their normal programming work. Is there a way you think the industry could be led to feasibly adopt that?
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9:26ivereadthesequel handmade_hero Had you seen the RLM parody of those "nerdbox" services that send you some cheap stuff in a box every month?
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9:26ivereadthesequel handmade_hero Had you seen the RLM parody of those "nerdbox" services that send you some cheap stuff in a box every month?
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9:26ivereadthesequel handmade_hero Had you seen the RLM parody of those "nerdbox" services that send you some cheap stuff in a box every month?
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10:33culdevu Q: I started my first programming job a couple months ago and have been thrown into an unfamiliar codebase a couple of times now. I wouldn't have said so previously, but now I'd say that the hardest part of learning a new codebase is the threading. That stuff can get crazy if it's not thought out carefully beforehand. Thoughts?
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10:33culdevu Q: I started my first programming job a couple months ago and have been thrown into an unfamiliar codebase a couple of times now. I wouldn't have said so previously, but now I'd say that the hardest part of learning a new codebase is the threading. That stuff can get crazy if it's not thought out carefully beforehand. Thoughts?
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10:33culdevu Q: I started my first programming job a couple months ago and have been thrown into an unfamiliar codebase a couple of times now. I wouldn't have said so previously, but now I'd say that the hardest part of learning a new codebase is the threading. That stuff can get crazy if it's not thought out carefully beforehand. Thoughts?
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19:30blaster_junior Q: Can you explain cache misses and how to avoid them? I'm coming from the Java world and never had to think about that
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19:30blaster_junior Q: Can you explain cache misses and how to avoid them? I'm coming from the Java world and never had to think about that
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19:30blaster_junior Q: Can you explain cache misses and how to avoid them? I'm coming from the Java world and never had to think about that
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22:07Modern Caches
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22:07Modern Caches
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22:07Modern Caches
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25:32The structure and work of an x64 CPU
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25:32The structure and work of an x64 CPU
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25:32The structure and work of an x64 CPU
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36:19x64 Scheduler out-of-order processing
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36:19x64 Scheduler out-of-order processing
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36:19x64 Scheduler out-of-order processing
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38:25x64 Caches1
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38:25x64 Caches1
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38:25x64 Caches1
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47:23Cache misses, and how to avoid them
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47:23Cache misses, and how to avoid them
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47:23Cache misses, and how to avoid them
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57:16IPC (Instructions Per Clock) vs. Cache Lines
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57:16IPC (Instructions Per Clock) vs. Cache Lines
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57:16IPC (Instructions Per Clock) vs. Cache Lines
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1:08:35Intel's undocumented L1 ← L2 "fill" penalty
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1:08:35Intel's undocumented L1 ← L2 "fill" penalty
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1:08:35Intel's undocumented L1 ← L2 "fill" penalty
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1:10:59Avoiding cache misses: 1) Learn cache sizes
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1:10:59Avoiding cache misses: 1) Learn cache sizes
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1:10:59Avoiding cache misses: 1) Learn cache sizes
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1:12:58Avoiding cache misses: 2) Organize for the cache
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1:12:58Avoiding cache misses: 2) Organize for the cache
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1:12:58Avoiding cache misses: 2) Organize for the cache
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1:20:16Avoiding cache misses: 3) Linear, simple access patterns (prefetching)
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1:20:16Avoiding cache misses: 3) Linear, simple access patterns (prefetching)
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1:20:16Avoiding cache misses: 3) Linear, simple access patterns (prefetching)
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1:26:07x64 Line buffers
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1:26:07x64 Line buffers
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1:26:07x64 Line buffers
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1:31:04Hyperthreading
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1:31:04Hyperthreading
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1:31:04Hyperthreading
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1:31:58Measuring cache utilisation with VTune or perf
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1:31:58Measuring cache utilisation with VTune or perf
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1:31:58Measuring cache utilisation with VTune or perf
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1:33:58saidwho12 Q: Is there a way to transfer data to the cache manually?
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1:33:58saidwho12 Q: Is there a way to transfer data to the cache manually?
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1:33:58saidwho12 Q: Is there a way to transfer data to the cache manually?
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1:34:39Intel's PREFETCH instructions2,3,4
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1:34:39Intel's PREFETCH instructions2,3,4
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1:34:39Intel's PREFETCH instructions2,3,4
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1:41:33Manual cache control in the Nintendo GameCube's Dolphin CPU and the Sony PlayStation 3
1:41:33Manual cache control in the Nintendo GameCube's Dolphin CPU and the Sony PlayStation 3
1:41:33Manual cache control in the Nintendo GameCube's Dolphin CPU and the Sony PlayStation 3
1:43:58saidwho12 Is 64 bytes the cache line size on every CPU?
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1:43:58saidwho12 Is 64 bytes the cache line size on every CPU?
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1:43:58saidwho12 Is 64 bytes the cache line size on every CPU?
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1:45:31sapper123 Q: Have you tested MeowHash on the new Zen2 processors?
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1:45:31sapper123 Q: Have you tested MeowHash on the new Zen2 processors?
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1:45:31sapper123 Q: Have you tested MeowHash on the new Zen2 processors?
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1:45:58printf_armin handmade_hero This is also important for DMA memory
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1:45:58printf_armin handmade_hero This is also important for DMA memory
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1:45:58printf_armin handmade_hero This is also important for DMA memory
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1:47:09kkrabz handmade_hero How does the processor handle multiple programs running at the same time, in regards to the cache?
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1:47:09kkrabz handmade_hero How does the processor handle multiple programs running at the same time, in regards to the cache?
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1:47:09kkrabz handmade_hero How does the processor handle multiple programs running at the same time, in regards to the cache?
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1:49:21The structure of a Zen CPU5
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1:49:21The structure of a Zen CPU5
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1:49:21The structure of a Zen CPU5
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1:53:12Yield and extreme ultraviolet lithography6,7
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1:53:12Yield and extreme ultraviolet lithography6,7
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1:53:12Yield and extreme ultraviolet lithography6,7
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1:55:06Chip fabrication8,9 and transistor density10
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1:55:06Chip fabrication8,9 and transistor density10
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1:55:06Chip fabrication8,9 and transistor density10
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2:10:11Failure in chip fabrication due to the sheer precision of the process11
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2:10:11Failure in chip fabrication due to the sheer precision of the process11
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2:10:11Failure in chip fabrication due to the sheer precision of the process11
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2:27:43Fabrication Yield and multiple cores
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2:27:43Fabrication Yield and multiple cores
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2:27:43Fabrication Yield and multiple cores
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2:37:14Cache Between Cores: 1) NUMA (Non-Uniform Memory Access) architecture
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2:37:14Cache Between Cores: 1) NUMA (Non-Uniform Memory Access) architecture
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2:37:14Cache Between Cores: 1) NUMA (Non-Uniform Memory Access) architecture
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2:43:38Cache Between Cores: 2) MESI (Modified, Exclusive, Shared, Invalid) protocol12
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2:43:38Cache Between Cores: 2) MESI (Modified, Exclusive, Shared, Invalid) protocol12
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2:43:38Cache Between Cores: 2) MESI (Modified, Exclusive, Shared, Invalid) protocol12
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2:48:40cultofrig Q: handmade_hero 64-byte lines are pervasive due to the burst size of DDR controllers. And yes, Arm also moved from 32-byte to 64-byte
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2:48:40cultofrig Q: handmade_hero 64-byte lines are pervasive due to the burst size of DDR controllers. And yes, Arm also moved from 32-byte to 64-byte
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2:48:40cultofrig Q: handmade_hero 64-byte lines are pervasive due to the burst size of DDR controllers. And yes, Arm also moved from 32-byte to 64-byte
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2:49:25rroohhh Q: The process for the silicon ingots is called Czochralski process
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2:49:25rroohhh Q: The process for the silicon ingots is called Czochralski process
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2:49:25rroohhh Q: The process for the silicon ingots is called Czochralski process
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2:49:37sanchopanzo handmade_hero Why don't they focus on increasing the cache sizes? Is there a hard limit to it or are they happy with the sizes as they are?
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2:49:37sanchopanzo handmade_hero Why don't they focus on increasing the cache sizes? Is there a hard limit to it or are they happy with the sizes as they are?
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2:49:37sanchopanzo handmade_hero Why don't they focus on increasing the cache sizes? Is there a hard limit to it or are they happy with the sizes as they are?
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2:51:05pythno Q: Isn't wavelength and size of electron kind of the same? Just different models?
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2:51:05pythno Q: Isn't wavelength and size of electron kind of the same? Just different models?
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2:51:05pythno Q: Isn't wavelength and size of electron kind of the same? Just different models?
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2:51:17printf_armin Q: Did have the privilege to wear one at Infineon. Really interesting experience
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2:51:17printf_armin Q: Did have the privilege to wear one at Infineon. Really interesting experience
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2:51:17printf_armin Q: Did have the privilege to wear one at Infineon. Really interesting experience
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2:51:35cubercaleb Q: If the probability of failure for one chip is P(F), and the probability of failure for two combined chips is denoted P(FC), then P(FC) = 2 * P(F) - P(F) * P(F)
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2:51:35cubercaleb Q: If the probability of failure for one chip is P(F), and the probability of failure for two combined chips is denoted P(FC), then P(FC) = 2 * P(F) - P(F) * P(F)
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2:51:35cubercaleb Q: If the probability of failure for one chip is P(F), and the probability of failure for two combined chips is denoted P(FC), then P(FC) = 2 * P(F) - P(F) * P(F)
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2:51:56Failure probability of two combined chips
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2:51:56Failure probability of two combined chips
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2:51:56Failure probability of two combined chips
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3:00:48cubercaleb Q: It's the union of either chip being a dud, minus the intersection of both chips being a dud (since this is already accounted for in the union)
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3:00:48cubercaleb Q: It's the union of either chip being a dud, minus the intersection of both chips being a dud (since this is already accounted for in the union)
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3:00:48cubercaleb Q: It's the union of either chip being a dud, minus the intersection of both chips being a dud (since this is already accounted for in the union)
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3:01:38cubercaleb Q: I over simplified. It should just be Bayes' theorem and these events should be independent, so just multiply the failure rate
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3:01:38cubercaleb Q: I over simplified. It should just be Bayes' theorem and these events should be independent, so just multiply the failure rate
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3:01:38cubercaleb Q: I over simplified. It should just be Bayes' theorem and these events should be independent, so just multiply the failure rate
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3:02:53Close this down
3:02:53Close this down
3:02:53Close this down